FPGA Simulation: A Complete Step-by-Step Guide

ASIC/FPGA verification has always been a mixture of various proprietary software and methodologies. However, with SystemVerilog, PSL, and OVM, verification is moving toward open source standard methodology. Today, ASIC/FPGA verification is where RTL design was in the early 90's.Are you an FPGA/ASIC engineer who has heard about assertions, SystemVerilog , and OVM? Are you looking for an easy, step-by-step book that will help your company and you move from direct test verification or lab verification to the modern advanced functional verification (AFV)?So. the big question from companies and engineers is, "What book can I buy to get me started with advanced functional verification?"This is the first book I have read that understands that companies and employees cannot just throw out their current verification methodology on Monday and start using advanced functional verification on Tuesday. This book begins by using ModelSim and code coverage, and each chapter progressively adds more AFV techniques. The book is written so that the user can determine how much AFV is appropriate for him/her and allows each user to remain at any step toward full AFV. For example, I liked the chapter that explained how I can start using assertion-based verification without upgrading the simulation software.Unlike so many other SV/OVM books I have read, this book assumes the user wants basic knowledge of AFV and is a guide to understanding an AFV system. The other books assume one already knows the information provided in this book.It is also very easy to read. I liked the fact that the chapters are short enough that one can easily read and finish a chapter while waiting for someone, on short bus trips, or in an airplane. The examples in the book are easy to understand and completely explained line-by-line, which I loved. The examples can also be downloaded.I highly recommend this book to anyone who wants to start using AFV. If you are an engineer who does not want to be left behind, get this book.

Didn't really show why FPGA simulation is different than non-FPGA simulation. And if not, then you don't need this book.

This book is way too generic. A big part of it consists of silly semi-personal "life" stories from the author. A lot of unrelated fat. Extremely boring and hard to read. Stuff that matters is not covered in details at all. This book is more like a joke. I think that you are much better off getting a book on System Verilog and ModelSim instead. Very disappointed.

At last a book that address advanced verification in a step by step manner for the FPGA community.FPGA designers all too often want to skip verification and just test hardware in the lab. They can always go back and re-programmed any bugs that they find.This book highlights where that strategy is no longer valid for today's large FPGA devices containing embedded processors, complex vendor cores and the end user's custom designed logic. Advanced functional verification can be pretty daunting when your EDA vendor comes along and tells you all that is whizz bang and new plus introducing a multitude of new languages, new methodologies, new acronyms & new verification techniquesRay's book is a great learning aid to help break down the barriers to adopting new verification techniques. It introduces the various concepts one piece at a time in short/sharp chapters. Each chapter is also full of coded examples that explain, in simple terms, exactly how each new technique is working.I also like that there is no prerequisite to be a SystemVerilog or OVM expert before you tackle the chapters or the examples. For VHDL folks, there is even an introduction to compiling verilog code and dealing with includes, etcI can definately see how this book will help many FPGA designers move up the verification sophisification curve by adopting some or all of the suggested steps.

As I was re-reading this book "FPGA Simulation" I realized, this is the best source of information I have right now (I have three books on SystemVerilog). The ideas in this book could be the key to finding my next consulting job. Let me go back a few months and tell you a story: After many calls and emails to Mentor Graphics regarding how to interface my VHDL based FPGA to a SystemVerilog TestBench, they put me in contact with the Author, Ray Salemi (one of their FAEs). He gave me chapters and I gave him feedback from my experience and in the process, I learned more about SystemVerilog language than ever before. I highly recommend this book, if you want to succeed, if you want to use SystemVerilog and if you see FPGA's as the future.

This book is great for a designer who wants to learn howto simulate and spend less time in the lab. It is asmooth read, well written with numerous examples that build uponprevious examples. I highly recommend this book.

It's a great book especially if you're looking for advanced verification techniques to your next FPGA design. Very well written with illustrating example codes.